- Engineers at UT Austin, in collaboration with TSMC, developed and tested an ultra-efficient SOT-MRAM chip for AI tasks.
- The chip was fabricated on a standard 300-millimeter wafer and demonstrated a 2-nanosecond write speed, 350 femtojoules energy, and a 166% TMR ratio.
- Tests indicated high efficiency in neural network inference, training binary neural networks, and modeling probabilistic graphs.
- Simulations revealed that device-to-device variation (about 10%) caused recognition accuracy to drop from 95.1% to 88%.
- Experts have noted that challenges remain in increasing stability, reducing variation, and addressing area penalty and integration issues.
- The new SOT-MRAM technology combines high speed, low power consumption, and the ability to retain data even when power is cut, which could significantly expand device capabilities in the future.
- SOT-MRAM's 2-nanosecond write speed is significantly faster than STT-MRAM's roughly 90 nanoseconds and PCRAM's roughly 50 nanoseconds.
- The energy consumption of SOT-MRAM at 350 femtojoules is several orders of magnitude lower than the hundreds of picojoules required by RRAM or the nanojoule-scale energy required by PCRAM.
- While SOT-MRAM is limited to two states, alternative memory technologies can create intermediate resistance values for more complex operations.
Engineers at the University of Texas, in collaboration with TSMC, have developed a groundbreaking 2-nanosecond SOT-MRAM memory chip designed for edge AI applications. This technology combines high speed and low power consumption, retaining data even when power is cut, which could significantly enhance device capabilities.10
During testing, the experimental chips demonstrated remarkable efficiency, with bit switching taking just 2 nanoseconds and requiring approximately 2 picojoules of energy. In contrast, alternative memory technologies can consume hundreds of picojoules and operate several times slower.1314
The SOT-MRAM memory's main limitation is its binary state storage (0 or 1), which necessitated adapting algorithms for AI tasks. The chips were tested in complex tasks, including neural network inference and training binary neural networks, showing potential for edge AI systems where calculations occur on-device.5
However, the technology faces challenges, particularly with device variation. Measurements indicated a 10% variation across devices, leading to a drop in recognition accuracy from 95.1% to 88% when variations were introduced. Experts are now focused on improving chip stability and reducing parameter variations to enhance accuracy.6789
The team fabricated an array of SOT-MRAM on a standard 300-millimeter wafer, achieving an average tunneling magnetoresistance ratio of 166% and confirming reliable magnetization switching with a pulse width of 2 nanoseconds at an operating voltage below 1 volt.234
Despite its advantages, SOT-MRAM cannot fully replace cloud computing for complex tasks requiring high precision, but it could significantly reduce energy consumption and processing time in edge AI applications.12
“The chip achieves 350 femtojoules per write, far lower than RRAM's hundreds of picojoules, and shows 0.1% write noise. However, simulations show that the measured 10% device-to-device variation reduces recognition accuracy from 95.1% to 88%, highlighting a key hurdle for real-world deployment.”
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