Intel’s new chip tech enables massive AI packages: how big can they get?

Intel is pushing the boundaries of AI chip design with new packaging technologies that enable significantly larger and denser AI chip packages.

The company introduced EMIB-T, an evolution of its Embedded Multi-die Interconnect Bridge (EMIB) technology, which adds thick vertical copper connections known as Through-Silicon Vias (TSVs) alongside the traditional fine horizontal interconnects. This innovation allows for more robust and compact inter-die communication.

Additionally, Intel showcased a low-thermal-gradient thermal compression bonding technique, a refined method for attaching silicon dies to organic substrates. This process supports the assembly of very-large substrates populated with multiple dies, increasing the overall chip package size and connection density.

"With Moore’s Law slowing down, makers of advanced and other data center chips are having to add more silicon area to their products to keep up with the relentless rise of AI’s computing needs," Intel noted.

These advancements are critical as AI workloads demand ever-increasing computational power, pushing chipmakers to innovate beyond traditional scaling. The new technologies enable connection densities down to about one every 25 micrometers, facilitating massive AI packages that could transform data center performance.

Intel’s developments signal a shift in chip architecture, focusing on multi-die integration and advanced bonding to overcome physical and thermal limitations, potentially setting new standards for AI hardware scalability.

Key quotes and stats:
- EMIB-T provides relatively thick vertical copper connections called TSVs.
- Low-thermal-gradient thermal compression bonding allows very-large substrates to be populated with dies.
- Connection density to EMIB can reach about one every 25 micrometers.

Intel is advancing chip technology with EMIB-T and low-thermal-gradient thermal compression bonding, enabling much larger AI chip packages. These innovations address Moore’s Law slowdown by expanding silicon area and increasing connection density, supporting the growing computational demands of AI in data centers.